Single Microwave Source

System Design

First of all, we wanted to build a simple source generating the microwave signal for our magnetic resonace experiments before we think of a more complex one. Hence, we started with the scheme depicted in Fig. 2. Here, a wideband programmable Voltage Controlled Oscillator (MAX2871) operates in a Phase Locked Loop (PLL) as a microwave source for signals from 23.5 MHz to 6 GHz (0.5 KHz resolution). In order to suppress high order harmonics arising from the frequency multipliers inside this chip, RF-filters have to be used. Due to the broad covered frequency range four different filters are required. The appropriate filter is selected by two SP4T RF switches. To adjust the RF output power a power leveling structure is used as depicted in Fig. 2. First, a programmable RF attenuator (PE43711) is able to lower the microwave power in steps of 0.25 dB. The subsequent fixed +12 dB broadband RF amplifier (TRF37A75) allows a total maximum output power of 10 dBm. A power calibration is realized by sampling the analog output voltage of the logarithmic power detector (LMH2110) and setting the appropriate amount of RF attenuation. The board reads commands from an USB 2.0 interface and requires an external 12 V DC input. The total cost of the assembeled PCB including all components amounts roughly 150 $.

Fig. 1. - Photo of the assembled PCB board with a description of the most important components.

Fig. 2. - Simplified system schematic of the single RF output version: Signal Source, Filterbank, Power Leveling and Microcontroller.

MAX2871 - Phase Locked Loop (PLL)

The heart of our RF source is the MAX2871 from Maxim Integrated®, a Fractional/Integer-N Synthesizer Phase Locked Loop (PLL). A PLL is required to stabelize the output signal of the VCO in the GHz range by using an adjustable feedback loop. The MAX2871 includes an PLL, which can be programmed to oscillate at any frequency between 23.5 MHz and 6 GHz. This chip requires a stable reference clock as an input. Thus a 19.2 MHz quarz oscillator is attached to provide fREF. The functional diagramm of a fractional PLL is shown in Fig. 3. Here, the reference clock is fed to a phase detector comparing the actual signal to the feedback signal from the VCO. A subsequent loop filter (LPF), externally realized on the PCB due to the size of the required components, supplies an analog voltage to the VCO proportional to the phase error of the detector. By changing the integer clock divider value N, the output frequency fVCO can be a multiple of the input frequency fREF. In order to attain fractional multiple values of the reference clock frequency the divider value N is rapidly switched between certain values. To keep in band noise and spectral spurs low this task is conducted by a Sigma-Delta modulation. A problem of wideband PLLs is the fact that VCOs with a good quality are not available for a wide frequency range. Thus, it is common to extend the frequency range by using in- and output-frequency multipliers creating disturbing high order harmonics. A second approach is the use of a VCO bank selecting the appropriate oscillator for the right frequency. The MAX2871 includes all the mentioned modules and can be programmed to fullfill the requirements of our application.

Fig. 3. - Functional Diagramm of a fractional PLL.

Digital Logic & Software

The RF source, RF switches, attenuator and ADC-converter have to be digitally controlled by a microcontroller. This task is executed by the PIC18F46J50, a high performance 8-bit microcontroller from Microchip®, clocked by a 12 MHz external crystal oscillator. This controller also features an on-chip USB 2.0 interface, allowing a straightforward connection to a computer. A serial port interface (SPI) is required to communicate with the RF source (MAX2871) and the programmable attenuator (PE43711). The used protocol is not standard and is implemented in-software. A snapshot of this SPI traffic is depicted in Figure 4. The right part of the signal configures the amount of attenuation in the (PE43711). The left part consits of 32-bits setting up the PLL chip. Two Latch Enable signals are used to latch the SPI data into each device respectivley. An additional I2C hardware interface is required to read out the analog sampling data from the 10-bit ADC (MCP3021), which is representing the total RF output power. Furthermore, the USB traffic has to be handled. The implemented controller Firmware reads commands from the USB bus, calculates the optimal PLL parameters and calibrates the output power. Sourcecode is written in C and compiled by the XC8 compiler suite from Microchip®. The PC control software works over a simple COM port interface, which can be easily addressed by a few MATLAB or Python commands.

Fig. 4. - SPI Traffic recorded by a Logic Analyzer.

Power Level Hierarchy

Another important aspect of the designed circuit is its power supply hierarchy, depicted in Fig. 5. Two synchronized step down switching regulators (L7980) create 5.0 V and 3.6 V from the 12 V input voltage, respectively. The 5.0 V output is directly used to supply the RF amplifier circuit. The 3.6 V rail is feeding various voltage regulators to provide a constant 3.3 V level for the remaining circuit components. First of all, the the microwave source chip is fed by an ultra-low noise low drop out (LDO) regulator. Additional ferrite beads minimize the total noise on this rail and provide a reliable power source for the MAX2871. The whole digital logic is powered by a standard 3.3 V LDO regulator. In order to supply voltage to the reference clock chip a 1.8 V LDO has been attached to the main 3.6 V rail. The total current consumption of the single RF source amounts 120 mA at 12 V input.

Fig. 5. - Functional Diagramm of the Power Supply Hierarchy.

PCB Layout & Manufacturing

The project has been realized in a 4-layer PCB stackup with a total thickness of 1.6 mm. The first internal plane is used as a continuous ground plane to secure a controlled impedance matching of the RF traces, the second internal plane serves as distributor for the 3.3 V power rail. Schematics and board layout have been designed with the open source EDA software KiCad. To attain a 50 Ω matching all RF traces have been set to a width of 0.34 mm. Furthermore, the resist on these traces has been removed to lower the total dispersion of microwave power. The first prototype has been assembled by hand using a solder paste stencil and a homemade reflow oven.

Fig. 6. - Board Layout rendered from KiCad.

Fig. 7. - Photo of the fresh PCB board.

Fig. 8. - Photo of the PCB board after reflow.

Oscilloscope & Spectrum Analyzer Measurements

In order to characterize the performance of the constructed circuit measurements with both oscilloscope and spectrum analyzer have been taken. A first check with a fast sampling oscilloscope shows a clean sine wave and the accuracy of the microwave frequency. For further investigation the data shown in Fig. 10 has been recorded by a spectrum analyzer. The first graph shows a detailed view of a 3 GHz output signal with a total bandwidth of 15 KHz. Spurs are also visible, but can be suppressed by using a different mode controlling the fractional PLL divider, in cost of a higher noise floor. Figure 6(b) shows the higher order harmonics of a 1 GHz output signal. Selecting the right RF-filter from the filter bank allows an efficient suppression of this unwanted components.

Fig. 9. - First test of the prototype with a 8 GHz oscilloscope.

Fig. 10. - (a) Spectrum of a 3 GHz signal for a output power of 0 dBm. Spurs arise from the fractional PLL mode. (b) Wide range spectrum of a 1 GHz signal. High order harmonics are visible, but suppressed by the appropriate RF filter.