# Dual Microwave Source V2

## Schematic Revision

This new revisions builds up on the schematic resources of the Dual Source. The biggest changes in this design are a more powerful microcontroller and an external clock input. The PIC18F67J50 with its high count of additional pins replaces the old microcontroller with the GPIO expander. Moreover, a new I2C external EEPROM allows the storage of user configuration and calibration data. In order to allow an synchronization of the microwave signals an extra SMA input allows the user to feed in an external clock. A subsequent RF-switch allows to switch between the Local Oscillator (19.2 MHz) and the external input (< 100 MHz).

Fig. 1. - Rendered 3D Model from KiCad.

Schematic. Click for PDF.

## Layout Revision

The new layout includes more space for the RF-traces and an ground shielding around the PCB outline and the two PLLs. Mounting holes for an aluminium case are also provided. Additionally, a 50 Ω matching at the output of the SMA connector for 6 GHz is attained by structuring the underneath ground layer. The geometry of this plane has been verified by a field simulation with CST Microwave Studio®.

Fig. 2. - Board Layout from KiCad.

## Power Supply Hierarchy

The basic power supply system is derived from the components of the Single Source. Here two synchronized step-down switching regulators create two basic voltage rails with 3.6 V and 5.0 V respectively. To assure a stable noise free supply for both PLLs two seperate ultra-low noise LDOs are used in combination with several ferrite beads. The digital logic is provided by a common 3.3 V switching regulator. The internal reference clock for the PLL requires an input of 1.8 V which is supplied by a respective LDO.

Fig. 3. - Functional Diagram of the Power Supply Hierarchy.

## New RF Power Detector Circuit

Except of the aforementioned changes, the old RF Power Detector Circuit has been replaced due to problems with its small BGA package and measurement gain. The new Power Detector LTC5532 features a higher precision and controllable gain within a frequency range of 300 MHz to 7 GHz. In order to measure the RF power at the output a splitter has to be designed. Due to the wide bandwidth a resistive tap is the best choice here. The coupling factor $A$dB of this structure can easily be calculated by using th internal impedance $R$IN of the detector IC:

$A$dB = 20 log(1 + R1/RIN)

The designed circuit aims for a coupling factor of 20dB, which is equivalent to $R$1=200 Ω (here $R$61). The value of this coupling factor is highly depended on the parasitics and accuracy of the chosen Resistor and its geometry in the layout. Luckily the LTC5532 allows an adjustable measurement gain. An additional output pin of this IC ($V$m) is a feedback to the inverted input of an internal op-amp. Therefore, the analog gain of the circuit can be controlled by the values of the feedback resistors $R$38 and $R$61 ($A=1+R$61/R38). The capacitor $C$150 is DC-block for the supply voltage of the RF-amplifier on the stripline.

Fig. 4. - RF Power Detector Schematic.

## PLL Loop Filter Design (LPF)

The basic function of the fractional PLL circuit was discussed in the section of the Single Source. The following will give a more detailed description of the designed PLL Loop Filter (LPF). A Loop Filter is used to convert the pulsed current output of the Charge Pump to a constant control voltage for the VCO. Therfore, this Filter has a low pass characteristic and additionally suppresses the reference clock frequency and its higher harmonics. Otherwise, unacceptably high spurious tones are present in the PLL output spectrum. Figure 5 shows an extract of the implemented MAX2871 PLL scheme. Here, the Loop Filter is marked with blue color and is connected between the CP_OUT and TUNE pin of the PLL chip. The filter connection to the SW pin is only required if the fast lock mode of the PLL is desired.

Fig. 5. - Schematic of the MAX2871 PLL Circuit.

The utilised circuit is a third order filter build up on passive components. Figure 6 shows the equivalent circuit diagram of this implementation. The first parallel branch with $R$1 and $C$1 transforms the current impuls from the charge pump to a usable voltage pulse. The subsequent components act as a low pass filter and aim for a constant voltage at the output to the VCO. This can be illustrated by calculating the transfer funtion in the frequency domain.

Fig. 6. - Third order passive Loop Filter.

The transfer function is calculated as the relation of the voltage at the VCO to the charge pump current at the input. The resulting term can be isolated according to its poles and nulls in the La Place plane. Where K is the time constant of the integral part and $\tau$z the constant which provides a stabilizing zero to the loop. The two poles are determined by the time constants $\tau$p1 and $\tau$p2 and suppress the tones of the 19.2 MHz reference clock and its higher harmonics.
The absolute value of this transfer function is displayed in Fig. 7. This Bode plot can be sperated into three general regions. The first region is the integral part, which provides the mechanism for the VCO to track the reference clock. A subsequent region of a nearly constant gain ensures stability by providing a big phase margin. In order to supress the high frequency components of the reference clock the last region experiences a big damping.

Fig. 7. - Bode Plot of the third order low pass loop filter.

## Manufacturing

In order to manufacture the first prototype a stencil for the top size of the PCB has been created. This allows a precise spreading of the solder paste and a subsequent reflow process in a homemade oven leaves us with the first working board.

Fig. 8. - Solder Paste spread on board.

Fig. 9. - Board inside the Reflow Oven.

Fig. 10. - PCB after reflow.

Fig. 11. - First Function Test.